Energy consumption in most digital integrated circuits is highly dependent on the supply voltage that powers the integrated circuits and on the frequency of the clock that controls the switching of the integrated circuits. Today's integrated circuits are able to operate over a wide dynamic range of both supply voltage and frequency, which can result in a widely varying range of energy efficiencies. In particular, the best energy efficiencies in digital CMOS silicon may be achieved around the “near-threshold voltage” (NTV) regime with an optimum supply voltage and frequency and a distinct minimum-energy point (MEP), where energy efficiencies can be 5-10× better than nominal supply operation. A key observation is that the optimum voltage and MEP can vary widely across workload activity and with process and temperature variations. Non-linear integrated voltage regulator (IVR) efficiencies can further shift MEP and optimum voltage, as the energy consumed by the entire system is taken into account. Finding a truly optimal MEP can make a significant difference in the energy consumed by the system.